Velaura AI Raises $110M Series A at $1B Valuation for Low-Power AI Silicon
Velaura AI has closed a $110 million Series A funding round at a valuation exceeding $1 billion. The financing was led by Seligman Ventures, with participation from Capricorn Investment Group alongside existing backers including Samsung Catalyst Fund, StepStone Group, Maverick Silicon, Celesta Capital, and Mayfield.
The capital will fund the commercialization and deployment of Velaura's silicon IP and physical design technology, which aims to reduce power consumption in data center accelerators, robotics, and edge computing hardware.
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| Standard GPU / AI Accelerator (~1000W) |
| +-------------------------------------+ +--------------------+ |
| | MATMUL / Matrix Engine (700-800mV) | | SRAM / HBM PHY / IO| |
| | Consumes ~60-70% Dynamic Power| | Consumes ~30-40%| |
| +-------------------------------------+ +--------------------+ |
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v
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| Accelerator with Velaura Titan Core IP (~500W) |
| +-------------------------------------+ +--------------------+ |
| | Titan Core Matrix Math (Sub-500mV) | | SRAM / HBM PHY / IO| |
| | 3x-4x Power Reduction in Math Core| | Standard Baseline| |
| +-------------------------------------+ +--------------------+ |
+-------------------------------------------------------------------+Voltage Scaling in AI Compute Engines
Modern large language model training and inference workloads are fundamentally dominated by dense matrix multiplications (GEMM/MATMUL). In state-of-the-art AI accelerators, these mathematical units draw the bulk of operational energy, running at typical operating voltages between 700 millivolts and 800 millivolts.
Because dynamic CMOS power dissipation scales quadratically with supply voltage (), reducing core operating voltage delivers disproportionate energy savings. However, operating deep sub-micron silicon at ultra-low voltages introduces timing variation, signal integrity challenges, and clock skew.
Velaura's proprietary architecture, designated Titan Core, provides custom standard cell libraries and optimized physical design layouts that allow the matrix compute units to function reliably at reduced supply voltages. According to company technical specifications, the platform achieves a 3x to 4x reduction in dynamic power within the matrix arithmetic blocks, resulting in up to a 50 percent reduction in overall chip-level power draw. On a standard 1,000-watt data center accelerator, this translates to power savings of up to 500 watts per socket.
Hardware Leadership and Industrial Heritage
Velaura AI was founded by Chief Executive Officer Rajiv Khemani and Chief Development Officer Manu Gulati. Khemani previously held leadership positions at Intel, Cavium, and Marvell. Gulati served as lead SoC architect at Apple and Google before co-founding NUVIA, the custom CPU startup acquired by Qualcomm in 2021 for approximately $1.4 billion.
The technical foundation of Titan Core stems from multi-year development at Auradine, where engineering teams designed high-throughput, low-voltage ASICs for cryptocurrency mining infrastructure. The mathematical structures used in high-density cryptographic hashing share architectural characteristics with the systolic arrays and tensor cores used in neural network processing.
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| Velaura Integration Flow |
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| Customer RTL Description (Verilog/SystemVerilog) |
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| v |
| Titan Core Synthesis & Cell Library Mapping |
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| v |
| Optimized Low-Voltage Physical Layout (GDSII / OASIS) |
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| v |
| Drop-in Integration into Host Accelerator SoC Flow |
+-----------------------------------------------------------------+Commercial Model and Deployment Scope
Rather than manufacturing standalone monolithic accelerators to compete directly with Nvidia, AMD, or hyperscaler ASICs, Velaura offers Titan Core as silicon IP and design integration services. The company takes existing customer register-transfer level (RTL) designs and remaps the compute blocks to its low-power physical implementation, maintaining functional equivalence while dropping voltage levels.
The company is targeting three primary compute tiers:
- Hyperscale AI Data Centers: Lowering thermal density, cooling requirements, and megawatt consumption in multi-gigawatt LLM training clusters.
- Physical AI and Robotics: Extending thermal envelopes and battery longevity in embodied systems running real-time vision-language-action (VLA) models.
- Edge Inference: Enabling low-latency local execution of quantized foundation models within constrained power budgets.
The new capital will support engineering expansion, customer-facing design integration teams, and tape-outs across advanced semiconductor foundry nodes.
