Navitas Semiconductor has entered into a definitive merger agreement to acquire power-management startup Claros in a deal valued at up to $232.8 million. The transaction brings vertical power delivery (VPD) and integrated voltage regulator (IVR) technology under Navitas's portfolio, targeting the physical bottlenecks limiting power transmission in modern AI hardware accelerators.
Under the agreed terms, Navitas will provide approximately $216.0 million at closing through a mix of cash and Class A common stock, with the remaining consideration contingent on Claros meeting specific operational and technical milestones over the subsequent two years. An additional $28.9 million in performance-based equity incentives is designated for continuing Claros staff. The transaction is expected to close before the end of 2026, subject to regulatory clearances.
The Last-Millimeter Power Bottleneck in AI Accelerators
Contemporary AI compute engines, spanning GPUs, TPUs, and custom neural processors, routinely draw over 1,000 watts per package while operating at sub-volt core levels. Under conventional server designs, voltage regulator modules (VRMs) are positioned laterally across the printed circuit board, feeding currents of several hundred to thousands of amperes sideways into the processor die.
This lateral topology creates severe constraints:
- I²R resistive losses: Large current paths across inches of PCB copper traces cause significant voltage drops and heat dissipation before reaching silicon gates.
- Transient response latency: High trace parasitic inductance limits how fast voltage regulators can ramp current during rapid changes in processor workload.
- PCB routing congestion: Wide power planes crowd out high-speed memory and interconnect routing around the accelerator socket.
Claros, founded in 2024 by Chief Executive Officer Dan Kultran with backing from investors including General Catalyst and Red Cell Partners, addresses this physical limitation by stacking power conversion stages directly underneath or integrated within the processor substrate. By moving voltage regulation to the underside of the package, the current transmission distance drops from several inches to millimeters. This vertical approach minimizes trace resistance, sharpens transient response, and frees PCB surface area for memory interfaces.
Grid-to-xPU Architecture and Commercial Strategy
Navitas specializes in wide-bandgap semiconductors, including gallium nitride (GaNFast) and silicon carbide (GeneSiC) power devices. These components are primarily deployed in grid-level conversion stages, rack-level power shelves, and high-voltage direct current (800V HVDC) data center architectures that step utility power down to intermediate server voltages.
Integrating Claros's IVR and VPD technologies completes what Navitas terms a "grid-to-xPU" power chain:
- Upstream conversion: High-voltage SiC and GaN stages convert 800V HVDC grid inputs to intermediate distribution rails inside the server rack.
- Downstream point-of-load: Claros integrated regulators step the intermediate bus voltage down directly at the compute core with minimal parasitic overhead.
According to Navitas, the acquisition expands its identified 2030 serviceable addressable market (SAM) to over $8 billion, adding an estimated $3.5 billion in addressable demand for vertical power delivery and integrated voltage regulators. Commercial deployments of the combined architecture are projected to scale from 2028 and 2029 onward, while Navitas continues rollouts of its 800V HVDC silicon carbide systems.
